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engineering specification type 15.0 sxga+ color tft/lcd module model name:N150P2-L04 document control number : oem N150P2-L04_1 note:specification is subject to change without notice. consequently it is better to contact to international display technology before proceeding with the design of your product incorporating this module. sales support international display technology engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 1/28 www..net
i contents i contents ii record of revision 1.0 handling precautions 2.0 general description 2.1 characteristics 2.2 functional block diagram 3.0 absolute maximum ratings 4.0 optical characteristics 5.0 signal interface 5.1 connectors 5.2 interface signal connector 5.3 interface signal description 5.4 interface signal electrical characteristics 5.4.1 signal electrical characteristics for lvds receiver 5.4.2 lvds receiver internal circuit 5.4.3 recommended guidelines for motherboard pcb design and cable selection 5.5 signal for lamp connector 6.0 pixel format image 7.0 parameter guide line for cfl inverter 8.0 interface timings 8.1 timing characteristics 8.2 timing definition 9.0 power consumption 10.0 power on/off sequence 11.0 mechanical characteristics 12.0 national test lab requirement engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 2/28
ii record of revision first edition for customer. (cable length:105mm) all oem N150P2-L04_1 december 16,2002 summary page document revision date engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 3/28
1.0 handling precautions if any signals or power lines deviate from the power on/off sequence, it may cause shorten the life of the lcd module. the lcd panel and the cfl are made of glass and may break or crack if dropped on a hard surface, so please handle them with care. cmos-ics are included in the lcd panel. they should be handled with care, to prevent electrostatic discharge. do not press the reflector sheet at the back of the lcd module to any directions. do not stick the adhesive tape on the reflector sheet at the back of the lcd module. please handle care when mount in the system cover. mechanical damage for lamp reflector, for lamp cable and for lamp connector may cause safety problems. small amount of materials having no flammability grade is used in the lcd module. the lcd module should be supplied by power complied with requirements of limited power source (2.5, iec60950 or ul60950), or be applied exemption conditions of flammability requirements (4.7.3.4, iec60950 or ul60950) in an end product. the lcd module is designed so that the cfl in it is supplied by limited current circuit (2.4, iec60950 or ul60950). the fluorescent lamp in the liquid crystal display(lcd) contains mercury. do not put it in trash that is disposed of in landfills. dispose of it as required by local ordinances or regulations. never apply detergent or other liquid directly to the screen. wipe off water drop immediately. long contact with water may cause discoloration or spots. when the panel surface is soiled, wipe it with absorbent cotton or other soft clothe; do not use solvents or abrasives. do not touch the front screen surface in your system, even bezel. gently wipe the covers and the screen with a soft cloth. the information contained herein may be changed without prior notice. it is therefore advisable to contact international display technology before proceeding with the design of equipment incorporationg this product. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by international display techlonogy for any infringements of patents or other right of the third partied which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of international display technology or others. engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 4/28
2.0 general description this specification applies to the type 15.0 color tft/lcd module 'N150P2-L04'. this module is designed for a display unit of notebook style personal computer. the screen format and electrical interface are intended to support the sxga+(1400(h) x 1050(v)) screen. support color is native 262k colors(rgb 6-bit data driver). all input signals are lvds(low voltage differential signaling) interface compatible. this module does not contain an inverter card for backlight. 2.1 characteristics the following items are characteristics summary on the table under 25 degree c condition: 0 to +50 -20 to +60 temperature range [degree c] operating storage (shipping) 105 typ. cfl cable length [mm] 8 pairs lvds(even/odd r/g/b eedid(clock, data) data(6bit), 3sync signals, clock) electrical interface backlight : 4.1 typ., 4.7 max. logic : 1.8 typ. (tbd) , 3.4 max. (tbd) power consumption [watt] design point 2:(icfl=6.5ma) +3.3 typ. nominal input voltage vdd [volt] 45 typ.,50 max. optical rise time/fall time [msec] 250 : 1 typ. contrast ratio 200 typ.(center), 185 typ.(5 points average) white luminance [cd/m 2 ] design point 2:(icfl=6.5ma) native 262k colors(rgb 6-bit data driver) support color normally white display mode 317.3(w) x 242.0(h) x 6.2(d) typ./6.5(d) max. physical size [mm] 615 max. weight [grams] r,g,b vertical stripe pixel arrangement 0.2175(per one triad) x 0.2175 pixel pitch [mm] 304.5(h) x 228.375(v) active area [mm] 1400(x3) x 1050 pixels h x v 381 screen diagonal [mm] specifications characteristics items engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 5/28
2.2 functional block diagram the following diagram shows the functional block of this type 15.0 color tft/lcd module. the first lvds port transmits even pixels while the second lvds port transmits odd pixels. j a e f i - x b 3 0 s l - h f 1 0 ( 3 0 p i n , l o c k t y p e ) x-dri ver t ft array/cell 6bit color data for r/g/b dt cl k(e ve n /od d) dsptm g hs yn c vs yn c vdd lcd controller lcd driv e ca rd backlight unit 1400(r/g/b) x 1050 gn d dc- dc converter ref c irc uit (e ve n /o d d) < 8 pairs lvds > even pixel odd pi xel dual lvds receiver lcd-drive connector y-driver g/a eedid chip v eedi d clkeedid dat aeedi d engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 6/28
3.0 absolute maximum ratings absolute maximum ratings of the module is as follows : rectangle wave g ms 50 18 shock g hz 1.5 10-200 vibration (note 1) %rh 95 5 hst storage relative humidity (note 1) deg.c +60 -20 tst storage temperature (note 1) %rh 95 8 hop operating relative humidity (note 1) deg.c +50 0 top operating temperature ma 20 - icflp cfl peak inrush current mams +7 - icfl cfl current (note 2) vrms +1,650 - vs cfl ignition voltage v vdd+0.3 -0.3 vin input signal voltage v +4.0 -0.3 vdd logic/lcd drive voltage conditions unit max min s y mbol item note 1 : maximum wet-bulb should be 39 degree c and no condensation . note 2 : duration : 50msec max. ta=0 degree c engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 7/28
4.0 optical characteristics the optical characteristics are measured under stable conditions as follows under 25 degree c condition: 200typ. center 185typ. 5 points average white luminance (cd/m 2 ) icfl 6.5 ma - 0.329 white y - 0.313 white x - 0.124 blue y - 0.158 blue x - 0.554 green y - 0.310 green x (cie) - 0.338 red y chromaticity - 0.577 red x color 50max 45 falling (ms) 50max 45 rising response time - 250 contrast ratio - - 15 30 vertical (upper) k 10 (lower) k:contrast ratio - - 40 40 horizontal (right) k 10 (left) viewing angle (degrees) note typ. specification conditions item engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 8/28
5.0 signal interface 5.1 connectors physical interface is described as for the connector on module. these connectors are capable of accommodating the following signals and will be following components. fi-x30m, fi-x30c2l mating receptacle/part number jae mating receptacle manufacture fi-xb30sl-hf10 type / part number jae manufacturer for signal connector connector name / designation sm02b-bhss-1 mating type / part number bhsr-02vs-1 type / part number jst manufacturer for lamp connector connector name / designation engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 9/28
5.2 interface signal connector roclkin+ 30 rein2+ 15 roclkin- 29 rein2- 14 gnd 28 gnd 13 roin2+ 27 rein1+ 12 roin2- 26 rein1- 11 gnd 25 gnd 10 roin1+ 24 rein0+ 9 roin1- 23 rein0- 8 gnd 22 data eedid (note 2,4) 7 roin0+ 21 clk eedid (note 2,4) 6 roin0- 20 reserved (note 1) 5 gnd 19 v eedid (note 2,3) 4 reclkin+ 18 vdd 3 reclkin- 17 vdd 2 gnd 16 gnd 1 signal name pin # signal name pin # (note) 1. 'reserved' pins are not allowed to connect any other line. 2. this lcd module complies with "vesa enhanced extended display identification data standard release a, revision 1" and supports "eedid version 1.3". 3. v eedid power source shall be the limited current circuit which has not exceeding 1a. (reference document : "enhanced display data channel (e-ddc tm ) proposed standard", vesa) 4. both clk eedid line and data eedid line are pulled up with 10k ohm resistor to v eedid power source line at lcd panel, respectively. engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 10/28
5.3 interface signal description lcd drive connector signal description ground gnd +3.3v power supply vdd odd lvds differential clock input roclkin+, roclkin- odd lvds differential data input (blue2-blue5, hsync, vsync, dsptmg) roin2+, roin2- odd lvds differential data input (green1-green5,blue0-blue1) roin1+, roin1- odd lvds differential data input (red0-red5, green0) roin0+, roin0- even lvds differential clock input reclkin+, reclkin- even lvds differential data input (blue2-blue5, hsync, vsync, dsptmg) rein2+, rein2- even lvds differential data input (green1-green5,blue0-blue1) rein1+, rein1- even lvds differential data input (red0-red5, green0) rein0+, rein0- description dual lvds mode signal name note : input signals shall be low or hi-z state when vdd is off engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 11/28
eedid data data eedid eedid clock clk edid eedid 3.3v power supply v eedid ground gnd power supply vdd horizontal sync: this signal is synchronized with dtclk. both active high/low signals are acceptable. hsync (h-s) vertical sync: this signal is synchronized with dtclk. only active high signal is acceptable. vsync (v-s) when the signal is high, the pixel data shall be valid to be displayed. +dsptmg (dsp) the signal is used to strobe the pixel +data and the +dsptmg (even/odd) data clock: the typical frequency is 81mhz. dtclk blue-pixel data: each blue pixel's brightness data consists of these 6 bits pixel data. (even/odd) blue data 0 (lsb) +blue 0 (eb0/ob0) blue data 1 +blue 1 (eb1/ob1) blue data 2 +blue 2 (eb2/ob2) blue data 3 +blue 3 (eb3/ob3) blue data 4 +blue 4 (eb4/ob4) blue data 5 (msb) +blue 5 (eb5/ob5) green-pixel data: each green pixel's brightness data consists of these 6 bits pixel data. (even/odd) green data 0 (lsb) +green 0 (eg0/og0) green data 1 +green 1 (eg1/og1) green data 2 +green 2 (eg2/og2) green data 3 +green 3 (eg3/og3) green data 4 +green 4 (eg4/og4) green data 5 (msb) +green 5 (eg5/og5) red-pixel data: each red pixel's brightness data consists of these 6 bits pixel data. (even/odd) red data 0 (lsb) +red 0 (er0/or0) red data 1 +red 1 (er1/or1) red data 2 +red 2 (er2/or2) red data 3 +red 3 (er3/or3) red data 4 +red 4 (er4/or4) red data 5 (msb) +red 5 (er5/or5) description signal name note: output signals except v eedid ,clk eedid and data eedid from any system shall be hi-z state when vdd is off. vsync should start with active high ( positive pulse ) signal from when vdd is supplied and its polarity should not be changed. engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 12/28
5.4 interface signal electrical characteristics 5.4.1 signal electrical characteristics for lvds receiver table . electrical characteristics mv +50 -50 vcm common mode voltage offset v 1.5 1.125 vcm common mode voltage mv 600 100 |vid| magnitude differential input voltage mv -100 vtl differential input low threshold mv +100 vth differential input high threshold conditions unit max typ min symbol parameter note: input signals shall be low or hi-z state when vdd is off. figure . voltage definitions engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 13/28
table . switching characteristics ps/clk 20 tcjavg cycle modulation rate(note) ps 700 thd data hold time fc = 54mhz, jitter < 50ps ps 700 tsu data setup time ns 19.6 18.5 17.5 tc cycle time mhz 57 54 51 fc clock frequency conditions unit max typ min symbol parameter note: this specification defines maximum average cycle modulation rate in peak-to-peak transition within any 100 clock cycles. this specification is applied only if input clock peak jitter within any 100 clock cycles is greater than 300ps. figure . timing definition (even) engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 14/28
figure . timing definition (odd) engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 15/28
figure . timing definition(detail a) engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 16/28
5.4.2 lvds receiver internal circuit below figure shows the internal block diagram of the lvds receiver. 5.4.3 recommended guidelines for motherboard pcb design and cable selection following the suggestions below will help to achieve optimal results. use controlled impedance media for lvds signals. they should have a matched differential impedance of 100ohm. match electrical lengths between traces to minimize signal skew. isolate ttl signals from lvds signals. for cables, twisted pair, twinax, or flex circuit with close-coupled differential traces is recommended. engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 17/28
5.5 signal for lamp connector lamp low voltage 2 lamp high voltage 1 signal name pin # engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 18/28
6.0 pixel format image following figure shows the relationship of the input signals and lcd pixel format image. even and odd pair of rgb data are sampled at a time . r g b r g b r g b r g b r g b r g b r g b r g b even odd even odd 0 1 1399 1st line 1050th line 1398 engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 19/28
7.0 parameter guide line for cfl inverter (ta=25 deg.c) note 2 w - 4.1 (tbd) 2.6 (tbd) - cfl power consumption(pcfl) (ta=25 deg.c) note 2 vrms - 630 (tbd) 720 (tbd) - cfl voltage (reference)(vcfl) (ta= 0 deg.c) note 3 vrms - - - 1,500 cfl ignition voltage(vs) (ta=25 deg.c) note 1 khz 60 40 cfl frequency(fcfl) (ta=25 deg.c) marms 7.0 6.5 3.5 3.0 cfl current(icfl) (ta=25 deg.c) cd/m 2 - - 200 185 (tbd) (tbd) - - white luminance (center) (5 points average) condition units max dp-2 dp-1 min parameter note 1: cfl discharge frequency should be carefully determined to avoid interference between inverter and tft lcd. note 2: calculated value for reference (icfl x vcfl = pcfl). note 3: cfl inverter should be able to give out a power that has a generating capacity of over 1,500 voltage. lamp units need 1,500 voltage minimum for ignition. note 4: dp-1 and dp-2 are recommended design points. *1 all of characteristics listed are measured under the condition using the test inverter. *2 in case of using an inverter other than listed, it is recommended to check the inverter carefully. sometimes, interfering noise stripes appear on the screen, and substandard luminance or flicker at low power may happen. *3 in designing an inverter, it is suggested to check safety circuit very carefully. impedance of cfl, for instance, becomes more than 1 [m ohm] when cfl is damaged. *4 generally, cfl has some amount of delay time after applying kick-off voltage. it is recommended to keep on applying kick-off voltage for 1 [sec] until discharge. *5 cfl discharge frequency must be carefully chosen so as not to produce interfering noise stripes on the screen. *6 reducing cfl current increases cfl discharge voltage and generally increases cfl discharge frequency. so all the parameters of an inverter should be carefully designed so as not to produce too much leakage current from high-voltage output of the inverter. *7 it should be employed the inverter which has 'duty dimming', if icfl is less than 4[ma]. engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 20/28
the following chart is cfl current versus the luminance for your reference. t. b. d. engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 21/28
8.0 interface timings basically, interface timings described here is not actual input timing of lcd module but output timing of sn75lvds86(texas instruments) or equivalent. 8.1 timing characteristics [dots] 1400 n data even/odd +data [usec] 12.96 thd display +dsptmg [tck] 24 8 thf h-front porch [tck] 300 64 26 thb h-back porch [tck] 250 56 8 tha [usec] 1.037 tha h-active level [tck] 1023 844 762 nh [usec] 15.63 th [khz] 63.98 fh scan rate +h-sync [lines] 1050 m v-line +dsptmg [lines] 1 1 nvf v-front porch [lines] 125 12 6 nvb v-back porch [lines] 62 3 1 nva [us] 46.7 15.78 tva v-active level [lines] 2046 1066 1058 nv [ms] 16.67 tv [hz] 60 fv frame rate +v-sync [ns] 18.5 tck [mhz] 57 54 51 fdck freqency dtclk unit max. typ. min. symbol item signal note:both positive hsync and positive vsync polarity is recommended engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 22/28
8.2 timing definition vertical timing 0.188 ms (12 lines) 0.047 ms (3 lines) 16.661 ms (1066 lines) 0.016 ms (1 line) 16.411 ms (1050 lines) 0.250 ms (16 lines) 1400 x 1050 at 60hz (h line rate : 15.63 us) tvb vsync back porch tva vsync width tv,nv frame time tvf vsync front porch m active field tvblk vertical blanking support mode tvblk m tvf tva tvb tv dsptmg -vsync +vsync horizontal timing 1.185 us (128 dots) 1.037 us (112 dots) 15.630 us (1688 dots) 0.444 us (48 dots) 12.963 us (1400 dots) 2.667 us (288 dots) 1400 x 1050 dotclock : 108.000 mhz (54.000mhz x2) thb hsync back porch tha hsync width th,nh h line time thf hsync front porch thd active field thblk horizontal blanking support mode thblk thd thf tha thb th dsptmg -hsync +hsync 0 2 4 n-4 n-2 video(even) video(odd) video(even) video(odd) dtclk 1 3 5 n-3 n-1 tck engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 23/28
9.0 power consumption input power specifications are as follows; mvp-p 100 allowable logic/lcd drive ripple noise vddns mvp-p 100 allowable logic/lcd drive ripple voltage vddrp all black pattern vdd=3.3v ma 540 (tbd) idd current idd max pattern vdd=3.6v ma 940 (tbd) idd current max idd max all black pattern vdd=3.3v w 1.8 (tbd) vdd power pdd max pattern vdd=3.6v w 3.4 (tbd) vdd power max pdd load capacitance 40uf v 3.6 3.3 3 logic/lcd drive voltage vdd condition units max typ min parameter symbol note: max pattern:2 dot vertical sub-pixel stripe. engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 24/28
10.0 power on/off sequence vdd power and lamp on/off sequence is as follows. interface signals are also shown in the chart. signals from any system shall be hi-z state or low level when vdd is off. 90% 10% 10% 10% 90% 10ms max. 0 min. 0 v 0 v vdd signals 180ms min. 0 min. 10% 10% 150ms min. 100ms min. 20ms min. lamp 90% 90% on (recommended). engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 25/28
11.0 mechanical characteristics engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 26/28
engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 27/28
12.0 national test lab requirement tbd ****** end of page ****** engineering specification (c) copyright international display technology 2002 all rights reserved. december 16,2002 oem N150P2-L04_1 28/28

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